Full-stack web applications and hardware down to the logic gate. Click any project to open its breakdown.
Team builds with a real frontend, a real backend, and a real database behind them. Click the card to open the breakdown, then visit the live site.
A complete point-of-sale platform for a bubble-tea shop: a customer kiosk, a cashier terminal, and a manager dashboard, all on one shared API and database. Deployed live on Render.
From combinational logic to a full ARMv8 datapath and a memory-system simulator. Click any card to open its breakdown.
A single-cycle ARMv8 processor in Verilog: fetch, decode, register file, ALU, data memory, and write-back, with a control unit decoding the 11-bit opcode. Extended with MOVZ to build full 64-bit constants, then verified with a self-checking testbench and run on FPGA hardware.
A configurable set-associative cache simulator reporting hit and miss statistics from memory traces. Designed an O(1) LRU replacement policy backed by a hash map and doubly linked list to study miss-rate tradeoffs across configurations.
A 4-bit combination lock implemented on the ZYBO Z7-10, using onboard switches as the input code and LEDs to indicate lock status. Verified correct on-board behavior by testing the Verilog compare logic and documenting required waveforms.
An infrared-based motion and presence alarm that activates a buzzer through comparator thresholding. Shared responsibility for circuit assembly, threshold calibration, and testing under varying ambient-light conditions.
A C++ client/server banking system over TCP sockets on Linux. The server accepts many clients at once and dispatches each request to a thread pool of persistent workers pulling from a task queue, with mutex-guarded shared account state and modular networking, finance, logging, and signal-handling layers.
Designed, simulated, and built a two-stage MOSFET amplifier on a ±5 V supply: a CD4007P common-source gain stage into a 2N7000G source-follower with a current-source bias. Hand-calculated the full bias, tuned it in Multisim, then verified it on hardware against gain, input-resistance, swing, and THD specs.
A sensor-aware traffic-light controller for a highway/farm-road intersection, built as a 6-state Moore FSM in Verilog. A 31-bit counter at 50 MHz times each phase, a farm-road sensor shortens the highway green, and the design was simulated then run on the ZYBO Z7-10.
A 4-bit arithmetic logic unit built from discrete 74-series ICs on a breadboard: a ripple-carry adder with XOR gates for add/subtract (two's complement), AND gates for bitwise AND, and a 2:1 MUX to select the operation. Verified against add, subtract, and AND test cases with LED outputs.
Whiteboard work and bench builds. I break problems down on paper, trace the signal flow, then validate on real hardware. Click any frame to enlarge.
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