ALI · HUSSEIN
INITIALIZING ENGINEERING INTERFACE
// MEMORY SYSTEMS

LRU cache, live

The same idea as my LRU Cache Simulator. Pick the geometry, enter a list of memory addresses, and step through to watch hits, misses, and least-recently-used eviction.

Access Hits 0 Misses 0 Hit rate 0%
// DIGITAL LOGIC

Gates & state machines

The building blocks of every chip. Flip the inputs to see a gate's output and truth table, then try the combination-lock state machine from my FPGA project.

Logic gate explorer
OUT = 0
Combination-lock FSM · code 1 · 3 · 2
LOCKED
S1
S2
OPEN
// NUMBERS & DECODERS

More logic toys

Flip bits and watch the numbers, the seven-segment display, and the adder update in real time.

Binary explorer · 8-bit
DEC 0HEX 0x00
7-segment decoder
4-bit ripple-carry adder
A
+
B