ALI · HUSSEIN
INITIALIZING ENGINEERING INTERFACE
// COMPUTER ARCHITECTURE

ARMv8 CPU Lab

An interactive single-cycle ARMv8 (LEGv8) processor, built from my Verilog CPU project with the same opcode encodings and control logic. Pick any instruction to see its assembly, colored binary fields, control signals, and C equivalent, then Step or Auto-run to watch it light up the active path through the datapath. Drag to pan, scroll to zoom, and click any component to open it in place: the ALU expands into a full adder, then logic gates, then real CMOS transistors with gate, source, and drain terminals. The register file, control unit, memory with cache, and sign-extend all open the same way. A second tab is a live C / Assembly / Binary editor with two-way translation and big or little-endian output.

// MEMORY SYSTEMS

LRU cache, live

The same idea as my LRU Cache Simulator. Pick the geometry, enter a list of memory addresses, and step through to watch hits, misses, and least-recently-used eviction.

Access Hits 0 Misses 0 Hit rate 0%
// DIGITAL LOGIC

Gates & state machines

The building blocks of every chip. Flip the inputs to see a gate's output and truth table, then try the combination-lock state machine from my FPGA project.

Logic gate explorer
OUT = 0
Combination-lock FSM · code 1 · 3 · 2
LOCKED
S1
S2
OPEN
// NUMBERS & DECODERS

More logic toys

Flip bits and watch the numbers, the seven-segment display, and the adder update in real time.

Binary explorer · 8-bit
DEC 0HEX 0x00
7-segment decoder
4-bit ripple-carry adder
A
+
B