I'm Ali Hussein, a Computer Engineering student at Texas A&M University. I design and verify digital systems, from ARMv8 datapaths and cache simulators to ASIC and FPGA logic, with a measure-and-verify mindset and a love for how complexity is built from clean building blocks.
I'm drawn to the layer where software meets silicon: datapaths, control logic, memory hierarchies, and the timing that makes them real. I like breaking systems into understandable parts, building them from clean reusable blocks, and proving they work with measurement instead of guesswork.
My focus areas are digital systems, computer architecture, RTL/Verilog design, and verification. Years of tutoring also taught me to explain complex ideas clearly, which is half the job on any engineering team.
Real engineering work, not buzzwords. Tap an area to see what it actually means and where it shows up in my projects.
Building a computer from the ground up: logic gates, MUXes, full adders, and finite state machines composed into a full ARMv8 datapath covering fetch, decode, execute, memory, and write-back. It's the difference between using a chip and understanding exactly how one works.
An ASIC (Application-Specific Integrated Circuit) is a custom chip built for one job. I work the RTL side of that flow: describing hardware in Verilog, then synthesizing and verifying it so a design could be taped out to silicon or programmed onto an FPGA.
Proving the hardware is correct before trusting it: directed testbenches, waveform inspection in GTKWave, on-board FPGA validation, and gdb step-through debugging for C/C++. The rule across every project, measure and verify, never guess.
Programming where software meets silicon: C/C++ and ARMv8 assembly, sensor and comparator interfacing, and circuit builds on real boards like the ZYBO Z7-10 and Raspberry Pi 4.
A cross-section of what I build, from a live full-stack web app to verified silicon. Click any card to open it, or open the full command center.
A full point-of-sale platform: a customer kiosk, a cashier terminal, and a manager dashboard on one shared API and database. Deployed live on Render.
A complete single-cycle datapath covering fetch, decode, register file, ALU, memory, and write-back, with control logic for R-type, load/store, and branch.
A configurable set-associative cache simulator with an O(1) LRU policy (hash map + doubly linked list) reporting hit/miss stats from memory traces.
An infrared presence detector that triggers a buzzer through comparator thresholding, calibrated and tested across varying ambient-light conditions.
Got a project, a question, or just want to talk shop about RTL, ASIC, and verification? Drop me a line.